For over a decade, the tech world has run on the backbone of a brilliant piece of engineering: the FinFET transistor. Its fin-like structure was a savior, allowing us to keep pace with Moore’s Law as we hit the limits of planar transistors. But now, as we push into the angström era (that’s 0.1 nanometers!), even the mighty Fin is running out of steam.

The next leap is here, and it’s not just an iteration—it’s a fundamental architectural shift. Welcome to the era of Gate-All-Around (GAA) Transistors.

For chip designers, this isn’t just a manufacturing curiosity. It’s a paradigm shift that unlocks new levels of performance and efficiency and introduces a new set of design rules. At Avecas Technologies, we’re already helping our partners navigate this transition. Let’s break down what GAA is, compare the two leading implementations from Intel and Samsung, and translate what it all means for the people designing the chips of tomorrow.

The “Why”: Hitting the Wall with FinFET

First, why now? The FinFET was brilliant because it raised the gate to wrap over three sides of a vertical silicon “fin,” giving it more control over the current flowing through the channel. This control meant less power leakage and more efficiency.

But as we shrank further, the fins became too narrow and close together. This led to electronic crosstalk and a loss of that critical gate control. Variability increased, and the performance gains we expected from each new node began to diminish. The industry needed a solution that provided even more gate contact with the channel.

Enter the Gate-All-Around transistor. For a deeper look at how we got here, explore our article on The Economics of Advanced Nodes.

The “What”: Gate-All-Around Transistors 101

The concept is as elegant as it sounds. Instead of a fin that the gate wraps around, the GAA transistor uses nanosheets or nanowires—tiny, horizontal ribbons of silicon—stacked on top of each other. The gate material is then deposited completely around each individual sheet.

This 360-degree contact gives the gate maximum control over the channel. The result?

• Dramatically Reduced Leakage: With superior control, less current escapes when the transistor is off.
• Higher Drive Current: More current can flow when the transistor is on, enabling faster switching speeds.
• Better Performance at Lower Voltage: You can achieve the same performance while using less power, a critical factor for mobile and battery-powered devices.

The “How”: Two Paths to the Same Goal – RibbonFET vs. MBCFET

While the core GAA principle is the same, the two leading implementations have key differences that designers need to understand.

1. Intel’s RibbonFET

Intel calls its GAA technology RibbonFET. It’s characterized by its use of horizontally stacked, nano-sheet silicon channels. The gate material is then wrapped around each ribbon, creating the namesake “gate-all-around” structure.

Key Design Characteristics:

• Nanoribbon Width: A key feature is that the width of these nanoribbons can be tuned. Wider ribbons provide higher drive current (for performance cores), while narrower ribbons optimize for power efficiency (for efficiency cores). This gives Intel, and designers using their process, a powerful knob to turn for specific applications.
• Back-Side Power Delivery: Intel is pairing RibbonFET with a revolutionary power delivery system called PowerVia, which moves the power delivery network to the backside of the wafer. This reduces signal interference and simplifies routing, a massive boon for designers battling interconnect complexity.

2. Samsung’s MBCFET™ (Multi-Bridge Channel FET)

Samsung’s approach, first to market with its 3nm node, is called MBCFET. While often used interchangeably with GAA, MBCFET specifically uses nanosheets rather than nanowires.

Key Design Characteristics:

• Sheet Width Control: Similar to Intel’s tunable ribbons, Samsung’s nanosheets allow for width modulation. This design flexibility is a core marketing point, allowing for customization for high-performance or low-power applications on the same chip.
• A Smoother Transition: Samsung has pitched its MBCFET as an evolution from FinFET, emphasizing that it allows designers to leverage existing design infrastructure and tools, potentially speeding up adoption and time-to-market.

RibbonFET vs. MBCFET: What’s the Real Difference?
At their core, they are fundamentally the same architecture. The difference lies in the implementation and the ecosystem. Intel is introducing a more holistic platform change with RibbonFET + PowerVia. Samsung’s MBCFET focuses on providing a more direct transistor-level upgrade from FinFET. For designers, the choice will come down to which foundry partner offers the best performance, power, and area (PPA) characteristics for their specific product. Understanding these foundry strategies is part of the larger trend of <a href=”https://www.avecas.com/blog/semiconductor-nationalism” target=”_blank”>Semiconductor Nationalism</a>.

What This Means for Chip Designers

This shift is more than just a physics problem for manufacturing teams. It has real implications for the entire design chain. At Avecas, our <a href=”https://www.avecas.com/services” target=”_blank”>ASIC and Design Services</a> are built to help you navigate these very challenges.

1. A New Set of PDKs: Designers will need to get comfortable with entirely new Process Design Kits (PDKs). These kits will have updated design rules, new standard cell libraries, and characterized cells built specifically for the GAA architecture.
2. The Power of Width Tuning: For the first time, designers will have the ability to select the channel width for different parts of their design. This adds a powerful new variable for optimizing circuits for maximum speed or minimal power consumption. This level of optimization is key to our <a href=”https://www.avecas.com/physical-design” target=”_blank”>Physical Design and DFT</a> methodologies.
3. EDA Tools Must Evolve: Electronic Design Automation (EDA) tools from Synopsys, Cadence, and others must be updated to model the complex 3D electrostatic properties of GAA transistors accurately. Simulation and verification will become even more critical.
4. A Renewed Focus on System-Level Co-Design: With the raw transistor performance seeing such a boost, the bottlenecks may shift elsewhere—to the interconnects and memory. This will push designers to think more holistically about architecture, memory hierarchy, and 3D packaging to fully leverage the transistor’s potential. This is where a <a href=”https://www.avecas.com/partnership” target=”_blank”>design partner</a> with expertise in full-stack optimization becomes invaluable.

Conclusion: The Next Chapter in Silicon

The transition from FinFET to Gate-All-Around transistors is a milestone on par with the move from planar to FinFET. RibbonFET, MBCFET, and future GAA variants are not just enabling the next process node; they are enabling the next decade of innovation.

For designers, it’s a call to arms. It demands learning new rules, leveraging new tools, and thinking about optimization in a more three-dimensional way. The companies and engineers who embrace this complexity first will be the ones designing the chips that power the AI, quantum, and immersive technologies of the future.

Is your design team ready for the GAA transition? The gate is now all-around, and the possibilities are wider than ever. <a href=”https://www.avecas.com/contact” target=”_blank”>Contact Avecas Technologies today</a> to discuss how our expertise can help you leverage these advanced nodes to build a competitive advantage.