Posted 4 months ago

Location: Hyderabad
Job Type: Full-time
Joining: Immediate Joiner Preferred
Experience Level: 2-7 years preferred

Job Overview:

We are hiring a Design for Test (DFT) Engineer to join our VLSI team and contribute to the development of robust and testable integrated circuits. In this role, you will be responsible for implementing DFT architectures and strategies to ensure high-quality and manufacturable SoC/ASIC designs. The ideal candidate should have a solid understanding of scan insertion, ATPG, boundary scan, and industry-standard DFT methodologies.


Key Responsibilities:

  • Define and implement DFT architecture for complex SoC and ASIC designs
  • Insert and validate scan chains, MBIST, LBIST, boundary scan, and other test structures
  • Generate and validate test patterns using ATPG tools to achieve high fault coverage
  • Collaborate with RTL and physical design teams to ensure DFT features are correctly integrated
  • Work with test engineers to bring up DFT features on silicon and support yield improvement
  • Perform timing analysis and debugging of DFT-related issues during synthesis and STA
  • Develop and maintain DFT flows and scripts for automation and efficiency

Key Skills & Tools:

  • Good understanding of digital design and DFT principles including scan insertion, MBIST, and ATPG
  • Hands-on experience with DFT tools such as Synopsys DFT Compiler, TetraMAX, Tessent, or equivalent
  • Experience with JTAG, IEEE 1149.1/6 standards and boundary scan architecture
  • Proficiency in scripting languages like TCL, Perl, or Python
  • Understanding of synthesis and timing closure flows
  • Familiarity with RTL design, simulation, and verification environments

Qualifications:

  • Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI Design
  • [1-3 / 3-5+] years of experience in DFT implementation for ASIC or SoC projects
  • Experience working with test and foundry teams is a plus

Why Join Us:

  • Opportunity to work on advanced DFT architectures and methodologies
  • Exposure to complete chip design and manufacturing lifecycle
  • Collaborative and technology-driven work culture
  • Competitive compensation and career advancement opportunities

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