Location: Hyderabad
Job Type: Full-time
Joining: Immediate Joiner Preferred
Experience Level: 2-7 years preferred

Job Description:

We are hiring a Design Verification Engineer to join our dynamic semiconductor team. The ideal candidate will be responsible for verifying complex RTL designs using industry-standard verification methodologies and tools, ensuring functionality, performance, and reliability.

Key Responsibilities:

• Develop and execute comprehensive test plans and verification strategies.
• Build reusable testbench components using SystemVerilog and UVM.
• Debug simulation failures and collaborate with design teams for issue resolution.
• Perform functional, assertion-based, and code coverage analysis.
• Contribute to the creation of verification IP and reusable environments.

Required Skills:

• Strong understanding of digital design and Verilog/SystemVerilog.
• Proficient in UVM methodology and object-oriented verification techniques.
• Experience with EDA tools such as VCS, ModelSim, QuestaSim, or Riviera-PRO.
• Familiarity with scripting languages (Python, Perl, TCL) is a plus.
• Good debugging and problem-solving skills.

Education & Experience:

• B.E./B.Tech or M.E./M.Tech in ECE/VLSI/Embedded Systems.
• 0–3 years of experience in Design Verification (Trained freshers may also apply).

Why Join Us?

• Work with leading-edge verification environments and industry-standard tools.
• Excellent learning and development opportunities.
• Friendly work culture and mentorship from senior engineers.
• Exposure to real-time SoC/ASIC/FPGA verification projects.

Send your updated CV to careers@avecas.in or simply fill the form below
Subject Line: Application for Design Verification Engineer – Hyderabad