Modern multi-voltage SoCs shut down inactive blocks to conserve battery. Designing these power-gated blocks requires strict UPF (Unified Power Format) specifications to ensure clean isolation and retention when crossing power domains.

Substrate Leakage, Clock Glitches, and Domain Crossing

When a power domain shuts down, its outputs can float to intermediate voltages, causing excessive leakage or logic glitches in active domains. Furthermore, state data in shut-down domains is lost unless specialized retention registers are inserted and sequenced correctly.

Isolation Cells, Level Shifters, and Retention Registers

DFT and physical design engineers implement UPF rules to govern multi-voltage power domains:

• Isolation Cells Insertion: Placing clamp logic at domain boundaries to hold signals at a clean state (0 or 1) during shutdown.
• Level Shifters Placement: Inserting level shifters at domain boundaries to convert signal voltages between different power rails (e.g. 0.8V to 1.2V).
• Retention Registers Strategy: Utilizing dual-rail retention cells to save internal register states before power shutdown.
• UPF 3.0 Power State Definition: Specifying comprehensive power states and transition logic to drive power-aware synthesis.

Power-Aware Verification and Synthesis Flow

Power intent is verified using Synopsys VC LP and Cadence Conformal Low Power. Logic synthesis is driven by Synopsys Design Compiler (with UPF) to insert isolation and level shifter cells automatically.

Conclusion

UPF-driven low-power signoff is essential for modern SoCs. Explicit power state mapping and automated isolation cell insertion prevent high leakage and logic errors in low-power systems.