Automatic Test Pattern Generation (ATPG) and Fault Coverage Optimization are the cornerstones of high-quality semiconductor manufacturing. As designs migrate to advanced process nodes, traditional stuck-at fault models are no longer sufficient to ensure zero-defect quality. Avecas provides high-performance ATPG services that utilize sophisticated fault models and compression techniques to achieve maximum coverage with minimum test data volume. We specialize in identifying “hard-to-detect” faults and optimizing patterns to reduce test time on the ATE, directly impacting your bottom line and product reliability.
Our services bridge the gap between complex design architectures and high-yield manufacturing.
We go beyond basic stuck-at testing to implement a multi-model fault approach. Our engineers target transition delay, path delay, bridge, and cell-aware faults to catch subtle manufacturing defects that occur at 7nm and below. This comprehensive strategy ensures that timing-related defects and intra-cell shorts are fully detected before shipment. Diverse fault modeling reduces the risk of Customer Returns (DPPM).
As transistor counts grow, test data volume can become unmanageable. We implement and optimize scan compression architectures (such as EDT or TestKompress) to achieve massive compression ratios. This allows for high-quality testing even on legacy ATE equipment with limited memory, significantly reducing overall test cost. Efficient compression scales test quality without increasing test time.
Avecas performs rigorous fault simulation to identify “untestable” or “undetected” logic areas. We analyze coverage holes caused by design constraints, black boxes, or complex clocking. By utilizing “test points” and custom functional patterns, we fill these gaps to reach the highest possible coverage percentages. Systematic gap analysis ensures no logic gate is left unverified.
High switching activity during ATPG can cause excessive IR drop and thermal stress. We generate power-aware patterns that limit toggle rates during shift and capture cycles. This prevents “false” test failures and ensures that the silicon remains within its physical safety limits during the testing process. Safe pattern generation protects silicon integrity during high-speed testing.
For massive SoC designs, we utilize a hierarchical ATPG flow (Core-based testing). By generating and validating patterns at the IP or block level and re-using them at the top level, we significantly reduce the memory overhead and compute time required for signoff. Hierarchical flows accelerate the turnaround time for complex SoC signoff.
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Advanced models detect at-speed failures that standard tests miss.
Your Partner for High-Yield, High-Quality Silicon
We support ATPG and Fault Coverage activities using industry-standard tools and proven methodologies to minimize DPM and maximize silicon quality.
Utilizing advanced fault models to detect intra-cell defects and timing-related failures, ensuring reliability at 7nm and below.
Implementing high-ratio compression techniques like Embedded Deterministic Test (EDT) to reduce test data volume and ATE time.
Identifying coverage gaps through statistical analysis and inserting Test Points (TPI) to enhance controllability and observability.
Converting and validating test patterns into production-ready formats such as STIL and WGL for seamless ATE integration.
designing advanced SoCs.
with specialized process needs.
demanding low-power solutions.
requiring safety-critical libraries.
