In modern semiconductor design, the sheer volume of logic gates makes traditional testing methods inefficient and costly. Scan Insertion and Scan Compression are fundamental DFT techniques that transform sequential logic into a testable state, allowing for rapid and thorough fault detection. At Avecas, we specialize in implementing high-efficiency scan architectures that balance maximum fault coverage with minimized test data volume. By utilizing advanced compression technologies, we help our clients significantly reduce test time on the ATE (Automated Test Equipment) while maintaining the highest quality standards for complex, multi-million gate SoCs.
Our services ensure that your design is optimized for manufacturing without inflating test costs or die area.
We perform automated scan insertion at the RTL or Netlist level, converting standard flip-flops into scan-replaceable cells. Our engineers meticulously manage clock domain crossing, scan-enable signals, and asynchronous resets to ensure a robust shift process. We optimize scan chain length and ordering to minimize routing congestion and power consumption. Precise insertion provides the foundation for high-quality structural testing.
To combat the rising costs of silicon testing, we implement industry-leading compression architectures such as EDT (Embedded Deterministic Test). By using decompressors on scan inputs and compactors on outputs, we reduce the number of required test pins and the total test data volume by 10x to 100x. Massive compression ratios enable high-test quality even with limited ATE resources.
For complex SoC designs, we utilize a hierarchical scan approach. By implementing scan and compression at the block or “wrapper” level, we allow for independent testing of individual IP cores. This modularity simplifies top-level integration and significantly reduces the turnaround time for ATPG and simulation. Hierarchical flows streamline the DFT process for massive, multi-core architectures.
Our team ensures seamless scan-stitching across multiple clock domains and power islands. We implement specialized synchronizers and lockup latches to prevent timing violations during the scan shift. This ensures stable data transfer across the entire chip, regardless of its architectural complexity. Robust clock management prevents data corruption during high-speed test operations.
Every scan implementation undergoes rigorous DRC (Design Rule Checking) and simulation. We verify scan chain integrity, shift functionality, and protocol compliance. Our sign-off process ensures that the inserted structures do not impact functional timing or power targets. Rigorous verification guarantees a “first-pass” success on the tester.
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Allows for high-quality testing using a very small number of physical test pins.
Your Partner for Optimized Manufacturing Test
We support Scan and Compression activities using industry-standard tools and proven methodologies to optimize test infrastructure and minimize manufacturing costs.
Automated transformation of sequential logic into scan chains with integrated compression logic to maximize fault coverage while minimizing area overhead.
Implementing IEEE 1500 compliant wrappers and hierarchical architectures to enable independent testing of complex IP cores within large SoCs.
Rigorous Design Rule Checking (DRC) and formal verification of scan protocols to ensure stable shift operations across all clock domains.
Sophisticated analysis and optimization of compression ratios to drastically reduce the data footprint and time required on the ATE.
designing advanced SoCs.
with specialized process needs.
demanding low-power solutions.
requiring safety-critical libraries.
