Analog layout

The engineering objective

Translate circuit intent into layout while controlling matching, parasitics, isolation and physical-rule compliance.

The work starts from schematics, PDK rules, device constraints, matching requirements and floorplan limits. The team should identify the authoritative revision of each input and record any assumptions needed to proceed. This prevents a later result from being interpreted against a different specification or configuration.

What needs technical attention

Passing DRC and LVS does not establish analog performance; extracted circuit behaviour must be checked against the specification.

The review centres on DRC, LVS, extracted performance, sensitive-node coupling and matching intent. Each finding should identify the input revision, observed behaviour and supporting evidence. Distinguish a confirmed defect from a configuration issue, an unsupported case or an open engineering question before deciding how to resolve it.

How the work is reviewed

The practical sequence is: plan device placement; implement matched structures and routing; extract parasitics; iterate layout against circuit and physical checks. Intermediate reviews allow the client to resolve decisions while changes are still manageable. If an input changes, identify the affected activities and repeat the checks that depend on it.

The expected package comprises layout database, extraction outputs, physical-check reports and layout review notes. Acceptance criteria should specify what the receiving team needs to reproduce, inspect or integrate these artifacts. Include known limitations and outstanding actions in that package, rather than assuming that delivery of a file implies acceptance.

Preserve electrical intent through models and layout

Analog results depend on operating conditions and modelling assumptions. Establish supply ranges, loading, bias conditions, temperature and the selected process models before comparing simulations. Identify which requirements concern nominal performance and which concern variation, startup, noise or stability. The intended use of each result should be clear: an exploratory sweep and a release check have different evidence requirements.

Layout choices can change the circuit through parasitics, coupling and device environment. Review matching intent, sensitive nodes, return paths, guard structures and routing symmetry with the circuit owner. A geometrically tidy layout is not necessarily an electrically suitable layout. Device placement and extraction results should be discussed together, especially when an observed shift is close to an acceptance limit.

When a model and a measurement disagree, first check units, configuration, instrument setup and the model’s range of validity. Use controlled sweeps to separate possible causes. Record solver settings, convergence concerns and any simplified boundary conditions. Circuit verification, layout verification and physical characterisation should retain their own acceptance criteria rather than allowing one successful check to stand in for all three.

An illustrative review scenario

A reference circuit may meet a nominal output target yet settle too slowly after a supply ramp. Review the ramp profile, load and initial conditions, then compare startup behaviour across the intended operating envelope. If extraction changes the result, identify the sensitive parasitic contribution before changing devices. This is a planning example and does not imply qualification of a specific technology.