RTL & architecture
Turn system requirements into clear microarchitecture, synthesizable RTL, and an integration plan.
Avecas IC design & embedded
ENGINEERING CAPABILITIES
IC design & embedded
engineering services.
Explore IC design and embedded engineering services across architecture, verification, implementation, and system integration.
Discuss your requirements
Representative photograph · Surface-mounted integrated circuits on a red circuit board.
THE ENGINEERING SCOPE
Built around
your requirements.
Design verification
Build confidence with verification planning, simulation, coverage analysis, and formal methods.
Physical design
Connect implementation decisions to timing, power, area, and physical signoff requirements.
Design for test
Plan test architecture, scan integration, ATPG, and the handoff to production test.
Analog & mixed signal
Support analog layout, integration, and verification across the agreed process and design rules.
Embedded & FPGA
Bring hardware and software together through prototyping, firmware, and system validation.
HOW WE WORK
Clarity at each stage.
01
Understand
Review the design challenge, available inputs, and target outcomes.
02
Scope
Agree the work package, ownership, interfaces, and delivery evidence.
03
Engineer
Execute with technical reviews and traceable issue resolution.
04
Deliver
Review the agreed sources, reports, and integration collateral.
PROJECT DECISIONS
Know what moves the work forward.
Use these gates to agree readiness, review evidence and responsibility at each stage.
- 01
Understand
What should be clear before progressing?
Review method and evidence
Review the design challenge, available inputs, and target outcomes.
Review evidenceAgree the owner, supporting artifacts and the decision needed to move to the next stage.
- 02
Scope
What should be clear before progressing?
Review method and evidence
Agree the work package, ownership, interfaces, and delivery evidence.
Review evidenceAgree the owner, supporting artifacts and the decision needed to move to the next stage.
- 03
Engineer
What should be clear before progressing?
Review method and evidence
Execute with technical reviews and traceable issue resolution.
Review evidenceAgree the owner, supporting artifacts and the decision needed to move to the next stage.
- 04
Deliver
What should be clear before progressing?
Review method and evidence
Review the agreed sources, reports, and integration collateral.
Review evidenceAgree the owner, supporting artifacts and the decision needed to move to the next stage.
ENGINEERING GUIDE
Plan IC design and embedded engineering services.
Read the technical guide
Choose a work package by its technical starting point
Use the directory to identify the engineering decision you need help with. An architecture question, an implementation task and a failing-system investigation need different inputs and different acceptance criteria. Start with the most specific discipline, then identify adjacent work that must be coordinated.
For a new chip or system, agree interface ownership before splitting the work across teams. For an existing design, provide the current baseline and the evidence behind the problem statement. Include known limitations and the environment in which the issue occurs. This helps distinguish a focused review from a larger redevelopment effort.
A useful first conversation ends with a proposed scope, prerequisites, deliverables and review points. The service pages describe typical engineering activities; the actual statement of work confirms available expertise, tooling, schedule and responsibilities. Contact Avecas with a short non-confidential summary before sharing protected design files.
Define the working agreement around technical outcomes
A useful engagement starts with a bounded problem and a named owner for the result. Separate technical scope, staffing assumptions and commercial arrangements. State which team owns architecture, implementation, integration and final acceptance. Identify external dependencies, including tools, licensed data, hardware availability and decisions that the client must provide before work can proceed.
Milestones should represent reviewable outputs. A schedule can show when an architecture review, implementation baseline, validation package or integration handoff is expected, together with the prerequisites for each. Track open decisions and their effect on downstream work. When the scope changes, revise the affected estimates and acceptance criteria rather than treating the change as an informal addition.
Plan for continuity after delivery. The receiving team should know which sources and reports are authoritative, how to reproduce key results and where limitations are recorded. Discuss the support period, issue triage and responsibility for integration separately from the initial delivery. Current staffing availability, location, lead times and commercial terms are confirmed for the actual engagement.
Build an engineering brief that teams can execute
A useful brief starts with the product decision, rather than a list of tools. Describe the intended application, the present design state and the next milestone. Separate constraints that are fixed from preferences that can change. For example, an existing package or board connector may be fixed while buffer depth, software scheduling or implementation hierarchy remains open. Give each constraint an owner so that a review can resolve tradeoffs without relying on assumptions.
For silicon work, identify the architecture baseline, interfaces, clocking, reset sequence, power intent and available technology collateral. Explain whether the engagement begins with a specification, RTL, a synthesized netlist, a placed design or fabricated devices. These starting points require different evidence. A verification team needs expected behaviour and an observable test interface; a physical implementation team also needs usable constraints and consistent library views. A test team needs the intended test modes, package connections and an agreed method for interpreting results.
For embedded work, include the processor or controller, board revision, boot path, operating environment, peripheral interfaces and available diagnostic access. State which failure modes matter to the application. A system that boots once on a development bench may still need recovery, update, endurance, timing and resource checks before release. Describe representative workloads and explain how the team will obtain logs when a failure occurs outside the laboratory.
Choose the engagement around ownership. A focused assessment can produce a finding register and a recommended next step. An implementation package requires agreed inputs, delivery artifacts and review gates. A broader turnkey programme needs explicit coordination between architecture, verification, implementation and downstream partners. Responsibilities for procurement, third-party IP, manufacturing, certification and final product acceptance should be recorded separately rather than assumed to be included.
Plan reviews around usable evidence. At the first gate, confirm that the inputs are complete enough to begin. During execution, review changes against the baseline and investigate unexpected results. At handoff, check that another engineer can identify the correct revision, reproduce the agreed checks and understand unresolved items. Deliverables should include configuration details and limitations alongside the output files. The receiving team should know who owns each remaining action.
Start the conversation with a short non-confidential summary through the contact page. Include the discipline, starting point, expected deliverable and target milestone. Avoid sending proprietary RTL, PDK files, customer data or credentials through a public form. Once the appropriate confidentiality and access arrangements are in place, the project team can agree a controlled method for sharing technical material and refining the estimate.
BEFORE WE BEGIN
Project questions.
A clear conversation is the start of a strong engineering relationship.
Can we start with a single work package?
Yes. A focused engagement can cover a particular design, verification, implementation, or integration requirement.
Which technologies and tools are supported?
The target process, IP, EDA tools, licenses, and engineering requirements are reviewed for each engagement before scope and schedule are committed.
PUT THE WORKFLOW IN CONTEXT
Explore the engineering decisions.
Practical reading to help prepare your project discussion. Studies are illustrative; they do not report client results.
What belongs in a turnkey IC-design project brief ↗ENGINEERING DIRECTORY
Find the right discipline.
Each guide explains the starting inputs, engineering sequence, checks and handoff for a defined work package.
102 engineering guides
- ADAS integration
Integrate sensing and compute pipelines around defined assistance functions.
- Advanced packaging engineering
Review interconnect and package integration for the intended assembly technology.
- AMS verification
Check interactions between continuous-time circuits and digital control.
- Analog circuit design
Develop circuits against gain, bandwidth, noise, power and operating-range requirements.
- Analog layout
Translate circuit intent into layout while controlling matching, parasitics, isolation and physical-rule compliance.
- Applied AI engineering
Integrate model behaviour into a measurable product workflow.
- Assembly and packaging
Evaluate package interfaces, interconnect requirements and thermal/mechanical constraints before assembly release.
- ATE programming
Integrate instrument resources, pin electronics and pattern execution.
- ATPG
Generate and debug patterns against agreed fault models.
- Automotive embedded systems
Coordinate embedded software and hardware within the vehicle-system boundary.
- AUTOSAR integration
Configure automotive software interfaces and platform services.
- AVF & in-house
engineering development.
Explore Avecas VLSI Flow: design configuration, stage orchestration, generated scripts, reports and engineering evidence.
- Battery-management software
Implement monitoring and control interfaces for a defined battery system.
- Boundary scan and JTAG
Enable controlled board and device test access through a documented test interface.
- CAD infrastructure
Make engineering environments reproducible and maintainable.
- CAD methodology engineering
Maintain repeatable flows and reference checks across engineering teams.
- Comparing engineering engagement costs
Compare complete engagement costs rather than headline hourly rates.
- Compliance preparation
Organise engineering evidence for the product's applicable assessment path.
- Custom silicon IP
Develop an integration-ready block around explicit interfaces, configurability, verification and implementation assumptions.
- Design for test
Plan and implement test access so manufacturing defects can be targeted without compromising functional operation.
- Design methodology
Make recurring engineering decisions and checks explicit in a reusable flow.
- Design verification
Build evidence that the design implements its specification across normal operation, boundary cases and error conditions.
- Device drivers
Connect hardware capabilities to an operating-system interface with controlled resource and lifecycle management.
- Device engineering
Evaluate device characteristics against the intended operating envelope.
- DFT architecture
Plan test modes and access before scan insertion.
- DFT verification
Check inserted test structures and protocols before pattern release.
- DSP algorithms
Develop signal-processing methods around measurable signal and compute requirements.
- DSP and AI acceleration
Map compute kernels to the right execution resources.
- ECO and closure
Apply controlled design changes while checking their functional and implementation impact.
- ECU software
Implement control-unit behaviour with defined diagnostics and communication.
- EDA flow automation
Turn a manual sequence into a controlled, inspectable engineering workflow.
- EDA integration
Connect tools through validated inputs, outputs and execution environments.
- EDA tool support
Investigate tool and environment issues using reproducible engineering cases.
- Edge AI
Deploy inference where connectivity, energy and latency constrain the system.
- Embedded AI
from model to edge system.
Support edge-AI implementation choices across model constraints, acceleration targets, memory limits, data movement, and deployment validation.
- Embedded hardware
Design electronic platforms around functional interfaces, component constraints and a measurable bring-up plan.
- Embedded machine learning
Fit model inference into a constrained software platform.
- Embedded middleware
Provide reusable services with clear resource and error-handling contracts.
- Embedded software
Build a software stack that respects hardware constraints and lifecycle needs.
- Embedded systems
Connect board-level hardware, firmware and application behaviour into a testable product architecture.
- Embedded testing
Combine component tests with hardware-backed integration checks.
- Engineering partnerships
Structure specialist support around a bounded technical problem and clear responsibilities.
- Engineering software
Build maintainable applications and automation around the real engineering workflow, access model and data lifecycle.
- Failure analysis
Isolate failure mechanisms through a staged investigation.
- Firmware development
Implement dependable device behaviour from startup through normal operation, updates and fault recovery.
- Formal verification
Use properties and exhaustive reasoning within a defined model and assumptions.
- FPGA and SoC integration
Partition functions across programmable logic and processors with explicit data movement and timing contracts.
- FPGA architecture
Partition logic, memory and interfaces to meet streaming and control goals.
- FPGA DSP implementation
Translate signal-processing operations into timed hardware pipelines.
- FPGA implementation
Bring a design onto a prototype board with observable interfaces.
- FPGA prototyping
Use programmable hardware to explore system behaviour and software integration.
- Functional-safety engineering
Support traceability and safety-related work products within an agreed development process.
- Hardware validation
Measure board behaviour against electrical and functional requirements.
- Hardware/software co-verification
Check the interface contract between software and hardware before release.
- IC design & embedded
engineering services.
Explore IC design and embedded engineering services across architecture, verification, implementation, and system integration.
- IP development services
Package custom logic for a defined integration and reuse model.
- Library and PDK engineering
Support library views and technology collateral used by implementation and verification teams.
- Library and PDK services
Organise and validate design libraries against agreed integration requirements.
- Logic synthesis
Map RTL into implementation cells under defined timing and area constraints.
- Low-power DFT
Coordinate test operation with power domains and isolation.
- Low-power implementation
Implement and verify power-control intent across the design flow.
- Low-power SoC design
Coordinate power states, hardware architecture and software policy.
- Manufacturing and test coordination
Connect design outputs with package, assembly and test requirements through an agreed partner and handoff model.
- Memory and logic BIST
Add self-test mechanisms suited to the memories and logic under test.
- One engineering plan.
From specification to handoff.
Bring design, verification, implementation, and delivery into a clearly scoped engagement. Agree the milestones, interfaces, and acceptance evidence before execution begins.
- Outsourcing VLSI engineering
Evaluate an external work package through scope clarity, evidence and integration ownership.
- PCB design
Translate schematic connectivity into a manufacturable board layout.
- PDK validation
Check technology collateral for consistency within the supported design environment.
- Physical design
Convert a constrained netlist into a placed and routed implementation while balancing timing, power, area and routability.
- Physical verification
Check layout connectivity and geometry against the selected rule decks.
- Post-silicon validation
Measure real-device behaviour against functional, performance and power requirements.
- Power and thermal design
Evaluate energy delivery and heat removal across operating modes.
- Power delivery network
Plan on-chip power connectivity around current demand and physical constraints.
- Process engineering support
Connect process-related data and design requirements through documented analysis.
- Production-test support
Bridge design test intent and tester execution.
- Project engineering
Coordinate technical dependencies and acceptance decisions across work packages and delivery teams.
- Reliability evaluation
Plan stress evaluation against defined product requirements.
- Research collaboration
& intellectual property.
Explore research collaboration, custom IP development, and the path from an engineering idea to a documented result.
- RTL and microarchitecture
Translate interface and performance requirements into synthesizable logic, register behaviour and a reviewable microarchitecture.
- RTL synthesis preparation
Prepare RTL and timing intent for a predictable mapped implementation.
- RTOS integration
Schedule concurrent work within measured timing and resource limits.
- Safety and security design
Translate product protection requirements into reviewable design and verification work.
- Scan and compression
Implement scan access with controlled chain balancing and compression.
- Semiconductor design
Plan custom silicon work around requirements, integration and implementation feasibility.
- Semiconductor engineering delivery
Structure semiconductor work with clear interfaces between the client and engineering team.
- Signal integrity
Assess interconnect behaviour for the intended edge rates and channel.
- Silicon bring-up
Establish first-device operation with a safe, observable sequence.
- Silicon engineering
Coordinate the engineering stages that turn architecture into implementation evidence.
- SoC integration
Connect IP blocks through consistent interfaces, address maps and system controls.
- Static timing analysis
Evaluate timing relationships across the agreed modes and corners.
- System architecture
Turn product goals into interfaces, budgets and responsibilities across hardware and software.
- System validation
Evaluate integrated behaviour against user and operating requirements.
- System-level test
Exercise silicon in representative system workloads.
- TCAD modelling
Set up device or process simulation studies with explicit physical assumptions.
- Technology models
Maintain model and technology references used by design tools.
- Test automation
Make repeated validation reproducible across hardware and software revisions.
- Test-program development
Translate a device test specification into a repeatable tester programme.
- Vision processing
Build image pipelines matched to the sensor and inference task.
- VLSI engineering staffing
Define specialist assignments around demonstrable skills and technical ownership.
- Wafer test
Define probing and electrical screening that separates devices into meaningful test bins before assembly.
- Yield and reliability engineering
Analyse product data with attention to variation, failure mechanisms and stress conditions.
- Yield engineering
Turn manufacturing test data into testable failure hypotheses.
YOUR NEXT CHAPTER STARTS HERE
What will you
build next?
Bring us your engineering challenge.
Let’s define the path from idea to implementation.