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- Silicon Engineering
- Packaging & Test
- Embedded Solutions
- Insights
- Company
At Avecas, our Wafer Test & Probe services ensure only Known-Good-Die (KGD) advance to packaging—reducing scrap, protecting assembly investment, and maximising final test yield.
Multi-Platform ATE Coverage
Teradyne J750, UltraFLEX, and Advantest V93000 for wafer sort and final test, with full multi-site probe card optimisation.
KGD & Speed Binning Expertise
We develop KGD programmes, speed-bin devices for performance-graded families, and correlate wafer map data with downstream yield.
Probe Card & Loadboard Engineering
End-to-end probe card design coordination, tip force optimisation, and electrical validation ensure full pin coverage across wafer lots.
Feel free to email us on below email address, we will be happy to answer your queries.
End-to-end probe card and loadboard bring-up with tip-force and planarity optimisation for stable contact across wafer lots.
Our wafer test capabilities span DC parametric, functional sort, speed binning, and KGD qualification—supported by probe card engineering and yield analytics.
Wafer sort is the first electrical gate in the back-end flow, screening every die before the cost of dicing and packaging is committed. Avecas builds sort solutions that maximise good-die identification, protect downstream investment, and feed clean data into yield engineering and reliability planning.
We develop and run DC parametric tests (Iddq, leakage, VDD ramp, continuity, opens/shorts), functional pattern-based sort using STIL/WGL patterns ported to the target ATE, multi-corner speed binning, and Known-Good-Die (KGD) programmes for bare-die shipment. Programs run on Teradyne J750 and UltraFLEX and Advantest V93000, with multi-site probe optimisation and parallel-site balancing to drive down cost per die.
Stable, repeatable contact is the foundation of trustworthy sort data. We coordinate probe card design (cantilever, vertical, and MEMS), tip-force and planarity optimisation, overdrive and cleaning strategy, alignment, and loadboard bring-up with full mechanical and electrical validation to ensure complete pin coverage across wafer lots, corners, and temperatures.
Wafer-map and bin data feed directly into yield analytics, giving early visibility into spatial and systematic defect signatures, while KGD screening with tightened limits and stress assist qualifies bare die for MCM, SiP, and 2.5D/3D integration with high confidence.
By catching defects at the wafer level, we reduce scrap, improve package yield, and surface process issues long before they reach assembly.
Wafer probe and sort questions arise frequently during NPI planning and HVM ramp. Here are answers to the most common questions our customers ask.