EXPLORE AVECAS
Perspectives on silicon design, verification, embedded systems, and the engineering decisions behind them.
May 23, 2026
Priority inversion is a silent, catastrophic bug in real-time operating systems. It occurs when a low-priority task holds a shared resource needed by a…
Read article Resolving Priority Inversion in RTOS-Based Embedded ArchitecturesMay 22, 2026
For highly time-critical applications like motor control, active safety systems, and RF transceivers, even the slight overhead of a C compiler can compromise interrupt…
Read article Bare-Metal ARM Cortex-M Assembly Optimization for Real-Time InterruptsMay 21, 2026
Cloud-dependent AI introduces latency, bandwidth, and security concerns for connected edge nodes. The ESP32-S3 microcontroller, equipped with integrated vector instruction extensions, enables fast, local…
Read article Deploying Deep Learning Models on ESP32-S3 using ESP-DLMay 21, 2026
VLSI offers many career paths, from RTL design to verification and physical design. This guide surveys the main roles, the skills they need and…
Read article Careers in VLSI: Roles, Skills and What Employers WantMay 20, 2026
Standard CAN networks, limited to 1 Mbps and 8-byte payloads, struggle to handle the high data demands of modern automotive ADAS and powertrains. CAN-FD…
Read article CAN-FD Protocol Optimization for High-Bandwidth Automotive NetworksMay 19, 2026
Traditional point-to-point wireless protocols struggle to maintain stable connections in complex, industrial smart environments. Thread, a secure, IP-based mesh network protocol, solves this by…
Read article Implementing Mesh Networks for IoT Nodes using Thread and OpenThreadMay 18, 2026
A handful of companies and regions dominate leading-edge manufacturing, while mature capacity is more widely spread. We survey the global foundry landscape at a…
Read article The Global Foundry Landscape TodayMay 18, 2026
Dynamic memory allocation in real-time operating systems (RTOS) must be fast, deterministic, and safe. FreeRTOS provides several heap management strategies, but complex, long-running systems…
Read article FreeRTOS Dynamic Heap Memory Managers: Comparing TLSF and Heap4May 17, 2026
Clock networks consume up to 40% of an ASIC’s dynamic power budget. Clock gating is the most effective logical optimization technique to minimize dynamic…
Read article Clock Gating and Multi-Bit Register Clustering for Low-Power DesignMay 16, 2026
At sub-5nm FinFET nodes, extremely thin gate oxides are highly vulnerable to dielectric breakdown. Designing robust Electrostatic Discharge (ESD) protection circuits for high-speed I/O…
Read article ESD Protection Circuit Design for Sub-5nm High-Speed InterfacesMay 15, 2026
South Wales hosts CSconnected, a compound-semiconductor cluster where research institutions and manufacturers concentrate expertise, showing how regional ecosystems can build defensible advantages in specialised…
Read article The UK’s Semiconductor Cluster in South Wales (CSconnected)May 15, 2026
Modern high-performance compute chips (such as GPU accelerators) rely on 2.5D and 3D packaging technologies to bridge processing units with High Bandwidth Memory (HBM).…
Read article Advanced 2.5D/3D IC Packaging Design and High-Density Interconnect Routing
