EXPLORE AVECAS
Perspectives on silicon design, verification, embedded systems, and the engineering decisions behind them.
May 3, 2026
Modern multi-voltage SoCs shut down inactive blocks to conserve battery. Designing these power-gated blocks requires strict UPF (Unified Power Format) specifications to ensure clean…
Read article UPF-Driven Power State Signoff: Isolation, Level Shifters, and RetentionMay 2, 2026
As silicon manufacturing moves down to the 3nm FinFET node, layout rules become incredibly restrictive. Physical verification engineers must deal with multi-patterning, fin-grid alignment,…
Read article Solving Complex 3nm FinFET DRC and LVS Rule Checks on Advanced NodesMay 1, 2026
The most advanced chips increasingly depend not on the transistor but on the package around it. CoWoS-class packaging has become a genuine capacity bottleneck.
Read article CoWoS and Advanced Packaging: Why Capacity Is the New BottleneckMay 1, 2026
The JTAG interface is a vital debugging tool from silicon bring-up to production. However, an unsecured JTAG port provides attackers with low-level read/write access,…
Read article Securing JTAG Debug Interfaces against Side-Channel and Hardware AttacksApr 30, 2026
Traditional place-and-route flows require hours of compilation to identify timing violations and routing congestion. Integrating Machine Learning (ML) into early design phases enables rapid…
Read article Using Machine Learning for Pre-Layout Timing and Congestion EstimationApr 29, 2026
In high-resolution data converters (12-bit and above), local variations in layout can ruin matching and degrade resolution. Custom analog layout design must employ advanced…
Read article Layout Matching Techniques for High-Resolution ADC and DAC DesignsApr 28, 2026
Imec, the Belgian nanoelectronics research hub, gives Europe a leading-edge research edge by pooling academia and industry around shared, extremely expensive advanced-process infrastructure.
Read article Imec and Europe’s Leading-Edge Research EdgeApr 28, 2026
The shift to PCIe Gen5 introduces massive data rates of 32 GT/s per lane, double that of Gen4. Implementing custom controller IP for this…
Read article Designing High-Speed PCIe Gen5 Controller IP for Enterprise StorageApr 27, 2026
Synopsys Design Constraints (SDC) are the core driver of logical synthesis and physical design. Inaccurate, loose, or overly restrictive SDC constraints can cause synthesis…
Read article Tuning SDC Constraints to Solve Setup and Hold Violations in SynthesisApr 26, 2026
Dynamic simulation can struggle to cover the astronomical state space of complex control logic such as arbiters, decoders, and cache controllers. Formal verification provides…
Read article Eliminating Complex Control Path Bugs with Formal Property CheckingApr 25, 2026
Intel 18A is central to the company's foundry comeback, aiming to regain process leadership with new transistor and power-delivery technologies.
Read article Intel 18A and the Foundry Comeback BidApr 25, 2026
As analog scaling pushes deep into sub-28nm and FinFET technologies, device dimensions approach atomic scales. In this realm, random local variations (mismatch) can severely…
Read article Monte Carlo Simulation Strategies for Sub-28nm Analog Circuits
