EXPLORE AVECAS
Perspectives on silicon design, verification, embedded systems, and the engineering decisions behind them.
Apr 24, 2026
Modern System-on-Chips (SoCs) operate across numerous modes—such as high performance, sleep, bypass, and test—across highly variable voltage and temperature corners. Standard Timing Analysis (STA)…
Read article Advanced STA Strategies for Multi-Corner Multi-Mode (MCMM) ClosureApr 24, 2026
The semiconductor industry is under constant pressure to deliver faster, smaller, and more efficient chips. With increasing design complexity and shrinking process nodes, traditional…
Read article AI Assisted RTL to GDS Flow How Machine Learning is Reducing Time to MarketApr 23, 2026
Universal Verification Methodology (UVM) is the gold standard for functional verification. However, poorly structured testbenches lead to low reuse, high compile times, and hard-to-maintain…
Read article Best Practices for Building Scalable UVM Testbenches for Custom IP BlocksApr 23, 2026
As data rates continue to increase across modern electronic systems, high speed SerDes design has become a critical component in industries such as data…
Read article Why High Speed SerDes Design Requires Advanced PCB Materials and Routing StrategiesApr 22, 2026
Developing modern 3nm ASICs involves handling billions of transistors, which exponentially increases test time and manufacturing costs. To keep tester usage economical, DFT engineers…
Read article Planning Scan Insertion and Compression Architecture for 3nm ASICsApr 22, 2026
The automotive industry is going through a major transformation driven by connectivity, automation, and intelligent systems. One of the key technologies accelerating this shift…
Read article The Rise of mmWave Technology in Automobiles for High Speed Wireless ConnectivityApr 21, 2026
The Last Frontier of Hardware Design In the semiconductor world of 2026, the stakes for a successful chip launch have never been higher. As…
Read article The Shift Toward Automated Post-Silicon Validation and High-Speed DebugApr 21, 2026
The Design-Linked Incentive scheme aims to nurture Indian fabless chip startups through financial support and design infrastructure; here is how it works and why…
Read article Design-Linked Incentive (DLI) Scheme: Boosting Indian Fabless StartupsApr 21, 2026
As data rates climb past 56 Gbps and 112 Gbps per channel, high-speed SerDes (Serializer/Deserializer) interfaces are pushing the limits of traditional PCB design.…
Read article Why High-Speed SerDes Design Requires Advanced PCB Materials and Routing StrategiesApr 20, 2026
The Breaking Point of Silicon For over half a century, Silicon (Si) has been the undisputed king of the semiconductor world. It powered the…
Read article How SiC and GaN Wide-Bandgap Semiconductors Are Transforming Power ElectronicsApr 18, 2026
Power, performance and area form the central trade-off in every chip design. This guide explains PPA and the choices engineers make to balance the…
Read article Understanding Power, Performance and Area (PPA) Trade-offsApr 18, 2026
The Persistent Soul of the Machine In the fast-paced world of semiconductors, digital logic often gets all the glory. We talk about billions of…
Read article The Analog Renaissance: Future Trends in Analog and Mixed Signal (AMS) Design
