In a synchronous chip, the clock is the heartbeat that keeps everything in step. But delivering that heartbeat to millions of flip-flops spread across a large die is surprisingly difficult. Clock tree synthesis, or CTS, is the stage of physical design dedicated to building the network that carries the clock signal everywhere it needs to go, as evenly as possible.

The Problem of Skew

If the clock reached every flip-flop at exactly the same instant, timing would be simple. In reality, wires have length and gates have delay, so the clock arrives at slightly different times in different places. This difference is called clock skew. Excessive skew erodes timing margins, can cause setup violations that slow the chip down, and in bad cases produces hold violations that make it fail outright. The goal of CTS is to keep skew small and predictable.

How CTS Builds the Tree

Rather than routing one impossibly large wire, CTS constructs a tree of buffers and inverters that fan the clock out in stages. Starting from the clock source, the tool inserts balancing buffers so that the delay to each endpoint, or leaf, is as similar as possible. The result resembles the branches of a tree, which gives the technique its name.

• Latency is the total delay from the source to the flip-flops, which CTS tries to control.
• Skew is the variation in that delay between endpoints, which CTS tries to minimise.
• Clock gating is added so unused parts of the chip can have their clock switched off to save power.

Balancing Skew Against Power

Modern systems-on-chip, or SoCs, complicate matters with multiple clock domains running at different frequencies, each needing its own balanced tree and carefully designed crossings between them. The clock network is also one of the largest consumers of dynamic power in a chip, because it switches on every cycle. Designers therefore balance the competing goals of low skew, low latency and low power, often using useful skew, where a small deliberate skew is introduced to help nearby logic meet timing.

Because CTS shapes both performance and power so directly, it is a stage where experienced judgement pays off. Practising clock tree construction and skew debugging on real design flows, as learners do in hands-on VLSI training at Avecas, builds the intuition that separates a competent physical designer from a novice.