Manufacturing a chip is an imperfect process. Dust particles, tiny misalignments and material flaws can leave defects in a small fraction of the transistors on any wafer. Since a modern chip may hold billions of transistors, manufacturers need a reliable way to sort good chips from faulty ones. The answer is to design the chip so it can effectively test itself, a discipline known as design for test, or DFT.

Why Testing Is Hard Without DFT

You cannot probe internal transistors directly once a chip is packaged. From the outside pins alone, it is nearly impossible to exercise every internal node. DFT solves this by adding special circuitry during design that makes the internal state observable and controllable from the outside, at the cost of a little extra area.

Scan Chains: The Backbone

The most widely used DFT technique is scan. During design, ordinary flip-flops are replaced with scan flip-flops that can be linked together into long shift registers called scan chains. In test mode, a tester shifts a known pattern of bits into the chain, runs the chip for one clock cycle, then shifts the results out to compare against the expected values. This turns the deep internal logic into something a tester can reach.

• Scan insertion stitches the flip-flops into chains during the design flow.
• ATPG, or automatic test pattern generation, computes the input patterns that will expose faults.
• Fault coverage measures the percentage of possible defects the patterns can detect.

ATPG and Fault Models

Testing every possible defect individually would be impossible, so engineers use simplified fault models, most commonly the stuck-at model, which assumes a node is permanently stuck at logic zero or one. ATPG tools automatically generate compact sets of patterns that achieve high fault coverage against these models, often above ninety-nine percent for critical designs. More advanced models catch timing-related and bridging faults that appear only when the chip runs at speed.

Built-in self-test, or BIST, goes a step further by embedding pattern generators and result checkers on the chip itself, useful for memories that need testing in the field. Together these techniques ensure that only genuinely working chips reach customers.

DFT is a specialised and well-paid corner of VLSI, and building scan chains and running ATPG on real tools, as students do in practical VLSI training at Avecas, is the best way to develop the skills employers look for.