Chiplets and UCIe: The Disaggregation of the SoC

Why the Monolithic SoC Is Breaking Up

For years the industry integrated ever more functionality onto a single large die. That strategy is now colliding with hard economics. Very large dies suffer disproportionately from manufacturing defects, so yield falls as area grows. Different functions also scale differently: logic benefits from the newest nodes, while analogue, I/O and SRAM often gain little from an expensive shrink. Disaggregating the SoC into multiple smaller dies, or chiplets, addresses both problems at once.

The Case for Chiplets

By partitioning a design into chiplets, each block can be built on the process node best suited to it, and smaller dies yield better. Known-good dies can be tested before assembly, and proven chiplets can be reused across product families. The result is a more modular, more economical approach to building complex systems, one that has already become mainstream in high-end CPUs and accelerators.

• Mix-and-match nodes: leading-edge logic beside mature I/O and analogue.
• Improved yield from smaller individual dies.
• Reuse of validated chiplets across multiple products.

UCIe: A Common Language for Dies

Disaggregation only works if chiplets can talk to one another reliably and efficiently. The Universal Chiplet Interconnect Express (UCIe) standard defines a common die-to-die interface, covering the physical layer, protocols and packaging assumptions needed for interoperability. The ambition is an open ecosystem in which chiplets from different vendors can be combined on a single package, much as boards are populated with standard components today.

Chiplets and UCIe together mark a shift from designing chips to composing systems, demanding fluency in packaging, interfaces and integration. Cultivating that broader systems perspective is a theme Avecas weaves through its VLSI training.