How Defence & Aerospace Sectors Depend on Indigenous Chip Design
Modern defence capabilities today extend far beyond traditional arms and ammunition. The real battlefield is digital, intelligent, and interconnected. From drones and satellites to missile systems and radar networks, every sophisticated defence platform relies on the silent force inside it: semiconductor chips. These chips operate as the central brain, enabling computation, sensing, navigation, communication, and […]
UVM 2.0 is Here: Streamlining Verification for Greater Reuse and Efficiency
The Accellera UVM 2.0 standard is finally here! Discover the key new features like the Phaser API, uvm_void’ roots, and how they boost verification reuse, debug, and efficiency for your ASIC projects.
Taming the Beast: The Unique Verification Challenges of AI/ML Accelerators
The AI revolution is being built on silicon. From data centers to edge devices, custom Neural Network Accelerators (NNAs) are the engines powering the incredible capabilities of large language models, computer vision, and more. But designing these beasts is only half the battle. Verifying them is a monumental challenge that pushes traditional methodologies to their […]
Shift-Left in Verification: How Emulation & Prototyping Find Bugs Earlier to Save Your Project | Avecas
In the high-stakes race to market for complex SoCs and ASICs, a late-stage bug discovery isn’t just a setback—it’s a potential project killer. A bug found at the tape-out stage can cost millions of dollars in re-spins, not to mention the irreplaceable loss of time and market window. For decades, the traditional verification flow has […]
No More Corner Cases: How Formal Verification is Becoming a SoC Verification Staple
For years, the world of ASIC and SoC verification has been dominated by dynamic simulation. We build massive, complex testbenches using UVM, write thousands of tests, and run them for billions of cycles, hoping we’ve thought of every scenario. But what about the corner case you didn’t think of? The rare bug that lurks in a state […]
The Path to 1nm and Beyond: Navigating the Next Frontier in Transistor Technology
The journey beyond 1nm is the next great semiconductor challenge. Explore the technologies—CFETs, 2D materials, and more—that will power future chips and how Avecas is preparing for the revolution.
The Chiplet Revolution: How Heterogeneous Integration is Breaking the Monolithic Mold
For decades, the relentless pursuit of Moore’s Law meant packing more and more transistors onto a single, monolithic piece of silicon. This “System-on-a-Chip” (SoC) approach delivered incredible gains. But today, at the bleeding edge of process nodes, the economics are breaking down. The cost of a new tape-out is astronomical, and yields for massive, complex […]
The Bleeding Edge Bill: Can We Afford the Astounding Cost of 3nm and 2nm Chips?
For half a century, Moore’s Law has been the beating heart of the tech industry. The prediction that the number of transistors on a chip would double every two years has given us exponentially more powerful smartphones, laptops, and cloud servers. We’ve come to expect it. But behind the scenes, a crisis is brewing. The […]
Semiconductor Nationalism: How the CHIPS Act and a Global Subsidy Race are Redrawing the Tech Map
For decades, the mantra of the global tech industry was efficiency above all else. Companies chased the lowest costs and the most streamlined supply chains, leading to an incredible concentration of a critical technology: semiconductor manufacturing. Today, that mantra is being replaced by a new, powerful word: resilience. The wake-up call was the pandemic-induced chip shortage, […]
The “Fab-Lite” Revolution: How Going Chipless Became a Smart Business Strategy
If you’ve followed the tech world in the last few years, you’ve heard the panic: “The global chip shortage is bringing industries to their knees!” Car manufacturers were parking unfinished vehicles, and gamers were battling bots for the latest graphics cards. In boardrooms, this chaos triggered a massive rethink. For decades, the gold standard for […]