Every modern chip begins life as text. Engineers describe its behaviour in a hardware description language such as Verilog or VHDL, producing what is called register-transfer level, or RTL, code. Physical design is the discipline that transforms this abstract description into a concrete geometric layout that a semiconductor foundry can actually fabricate. That final layout is delivered in a standard file format known as GDSII, which is why the journey is commonly called the RTL-to-GDSII flow.

What Physical Design Really Means

Physical design sits after logic synthesis, where RTL is converted into a netlist of logic gates. The physical designer’s job is to decide where each of those millions of gates should physically sit on the silicon, and how the wires connecting them should run. Getting this right determines whether the chip meets its speed, power and area targets, and whether it works at all.

The Main Steps

The flow is usually broken into a sequence of well-defined stages:

• Floorplanning defines the chip’s overall shape, the placement of large blocks, and the location of input/output pads and power rings.
• Placement positions the standard cells, balancing density against timing and routability.
• Clock tree synthesis builds a balanced network to deliver the clock signal to every flip-flop with minimal skew.
• Routing draws the metal interconnect that physically wires the cells together across multiple layers.
• Sign-off verifies timing, power integrity and manufacturing rules before tape-out.

Why It Is So Challenging

Physical design is a constant balancing act. Placing cells close together shortens wires and improves speed, but crowds the layout and creates routing congestion. Adding buffers fixes timing but consumes power and area. Modern tools from vendors such as Synopsys and Cadence use sophisticated optimisation algorithms, yet skilled engineers remain essential to guide the tools, interpret reports and resolve violations that automation cannot untangle on its own.

Throughout the flow, designers repeatedly run static timing analysis and design-rule checks, iterating until the layout is clean. Only then is the GDSII file handed to the foundry, where it becomes the blueprint for the photomasks used in manufacturing.

Understanding this flow end to end is the foundation of a career in chip design, and hands-on practice on real industry tools is the surest way to build that intuition, which is exactly what guided, lab-based VLSI training at Avecas is designed to provide.