DFT, Scan and ATPG: How Chips Test Themselves
Design for test, scan chains and ATPG let manufactured chips check themselves for defects. This beginner guide explains how testability is built into silicon.
GAA Transistors: RibbonFET and MBCFET Explained
The FinFET has reached its practical limit. Gate-all-around transistors, marketed as RibbonFET and MBCFET, are the industry’s answer for the 2nm generation and beyond.
Why the UK Bet on Compound Semiconductors, Not Leading-Edge Fabs
Britain chose to specialise in compound semiconductors instead of chasing leading-edge silicon fabs, a niche strategy that trades scale for differentiated, high-value technology and defensible expertise.
ATMP/OSAT vs Front-End Fabs: India’s Pragmatic Entry Strategy
India’s chip strategy prioritises ATMP and OSAT assembly and test over leading-edge fabs, a pragmatic entry route with lower capital risk and faster returns.
Micron’s Sanand ATMP Plant and India’s Memory Ambitions
Micron’s assembly and test plant at Sanand marked a milestone for foreign investment in Indian semiconductor manufacturing and signals early steps toward memory ambitions.
Siemens Unveils Agentic AI Toolkit to Accelerate IC Design and Verification
Siemens has introduced a new agentic AI driven capability within its Questa One platform, aimed at accelerating integrated circuit design and verification workflows as semiconductor complexity continues to rise. The move reflects the industry’s growing reliance on intelligent automation to manage advanced node designs, multi-die architectures, and increasingly demanding verification requirements. The latest enhancement brings […]
Clock Tree Synthesis: Balancing Skew in Modern SoCs
Clock tree synthesis distributes the clock across a chip while minimising skew. This guide explains why balanced clocks matter and how CTS achieves them in modern SoCs.
Chiplets and UCIe: The Disaggregation of the SoC
The monolithic system-on-chip is giving way to assemblies of smaller dies. Chiplets and the UCIe standard are quietly reshaping how complex silicon is built.
The UK Semiconductor Strategy Explained
The UK Semiconductor Strategy set out how Britain intends to strengthen its position in chips, focusing on design, research and compound semiconductors rather than large-scale leading-edge fabrication.
India Semiconductor Mission 2.0: Strategic Shift Towards Global Leadership and Indigenous Innovation
The Indian semiconductor landscape is entering a transformative new phase. With the recent unveiling of the India Semiconductor Mission (ISM) 2.0 in the Union Budget 2026–27, the government has signaled a shift from foundational capacity building to achieving deep technological sovereignty and global supply chain integration. The Evolution: From ISM 1.0 to 2.0 While ISM […]