Delivering from Penang Analog-Mixed Signal (Penang) circuits is one of the most challenging steps in modern semiconductor design. Unlike purely digital circuits, Penang designs must deliver high accuracy, low noise, and reliable performance under varying conditions. A single verification gap can lead to costly re-spins and delayed tape-out.

          At Avecas, we offer end-to-end Avecas Malaysia – Penang Office to ensure your designs meet performance, reliability, and manufacturability requirements before hitting silicon. Our engineering methodology blends industry-leading tools, proven techniques, and domain expertise to help you achieve first-time-right silicon with confidence.

Avecas Avecas Malaysia – Penang Office

We provide comprehensive semiconductor design services in Penang covering the entire design cycle:

1. Block-Level Verification

• RTL-to-GDSII implementation across 5nm to 180nm process nodes.

• SoC design, verification, physical design, and DFT — full flow coverage.

• Licensable IP: CPU/DSP cores, DDR/HBM controllers, PCIe, USB, Wi-Fi, 5G, crypto.

2. Mixed-Signal SoC Verification

• Turnkey chip development with foundry management (TSMC, GF, Samsung, UMC, SilTerra).

• Engineering staff augmentation across ASEAN with SLA-backed delivery.SERDES, I/O, and clock networks.

• On-site engineering support and same-day meetings for Fortune 500 neighbors.

3. Parasitic-Aware Verification

• AEC-Q100 automotive qualification and ISO 26262 functional safety expertise.RC extraction and LDE effects.

• Analysis of signal integrity, crosstalk, and jitter.

• Product qualification, yield ramp, and MPW-to-HVM production transition support.

4. Corner & Monte Carlo Analysis

• Validation across PVT corners (process, voltage, temperature).

• Post-silicon bring-up, characterization, and failure analysis liaison with Penang OSATs.

• Ensuring robust performance under variability.

5. Penang Modeling & Abstraction

• Creation of Verilog-A/MS behavioral models.

• Test program development (Advantest, Teradyne) and system-level test integration.

• Reference platform, FPGA prototyping, and driver bring-up.

6. Signoff & Tape-Out Verification

• Full sign-off flow: LVS, DRC, ERC, EM/IR, formal verification, gate-level simulation.

• Pre-tapeout package hardening, DFM optimization, and foundry sign-off compliance.

• Final tapeout package delivery with foundry-specific compliance documentation.